This invention relates to MOS gated devices, and more specifically relates to a novel process which exploits the different implantation ranges of certain N and P impurities to produce a junction pattern with fewer mask steps and only two critical mask alignments.
MOS gated devices, such as power MOSFETs, Insulated Gate Bipolar Transistors (IGBTs) and MOS gated thyristors are well known. The process used for the manufacture of these devices employs a sequence of masking steps in which many of the masks must be carefully and critically aligned with respect to one another. Each mask layer in a process increases manufacturing expense, and each mask step introduces a new possible source of defects. Moreover, the requirement of aligning several masks with critical accuracy relative to one another also adds manufacturing costs and introduces the possibility of additional manufacturing defects.
A process for manufacturing such devices which employs a reduced number of masks, and a reduced number of critical alignments between masks is desirable since it reduces wafer handling, potential defects and the cost of the individual chips in a wafer.